Samsung’s HBM4E Reliability Yield Surpasses 70%

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Samsung has achieved a key milestone in the development of its next-gen HBM chips. The company has increased the reliability test yield of its HBM4E to more than 70%. This suggests the chip could soon enter the stable production stage.
Samsung’s HBM4E development gains momentum
A few weeks ago, Samsung confirmed the shipment of 12-layer HBM4E samples to major global customers for evaluation. While it remains unclear what feedback the company has received from its clients, the development appears to be progressing in the right direction.
Samsung Chief Technology Officer (CTO) Song Jae-hyuk recently shared the progress during an internal management briefing. He said the reliability test yield for HBM4E has surpassed 70%. In the industry, a yield of 80% or higher suggests the chip has reached maturity. This means the Korean firm’s next-gen HBM solution is not far from reaching that level.
Samsung’s 12-layer HBM4E offers a stable pin speed of 14 Gbps and can scale up to 16 Gbps. It uses a 6th-generation 10-nanometer (nm)-class DRAM process (1c) and a 4nm logic base die. The chip will support the increasing demands of AI computing and hyperscale infrastructure.
Samsung aims to supply HBM4E for Nvidia’s Vera Rubin AI accelerator, which will launch in the second half of this year. The company also plans to supply the memory for Nvidia’s next-gen Vera Rubin Ultra AI accelerator, slated for release in 2027.
Meanwhile, Samsung is improving its 10nm-class 7th-generation (D1d) DRAM process. CTO Song said that the company plans to complete its internal Production Readiness Approval (PRA) in November. The D1d process may play a big role in the firm’s future HBM5 chips.
As Samsung continues to improve HBM4E and stabilize its D1d process, the company is bolstering its technological competitiveness in next-gen AI memory. It will be interesting to see if the firm succeeds in narrowing the gap with HBM market leader SK Hynix in the coming years.
















